A RAM-based Neural Network Architecture for Wafer Scale Integration
نویسندگان
چکیده
While the use of WSI technology to increase the integration density of RAM devices may not be cost effective (cf. Anamartic’s failed WSI RAMs [23]), low defect tolerance overheads, high testability, and low power consumption make memories ideal building blocks for WSI processor architectures. Indeed, this is reflected in the number of memory-based WSI devices manufactured to date [15,19,22,23,24].
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